Projekte

FPGAs in the medium and high price/performance segment today usually have serial transceivers with a transmission rate of several Gbit/s. With these transceivers, the clock signal required to read the data is reconstructed from the data stream, e.g. using a PLL. This eliminates the need for a dedicated clock line, which greatly simplifies transmission over longer distances. In the case these transceivers are not available (e.g. for cost reasons), alternative approaches must be used.

As part of this project, a serial data link with an embedded clock signal was implemented based on a Lattice ECP5 FPGA without transceivers. The modules for clock recovery, 8B/10B data coding and error detection have been implemented in the programmable logic, which allows for future porting to other FPGA variants. On the physical level, a direct LVDS connection was established via a simple ribbon cable with a length of 50 cm.

In the implementation described, a stable data connection with a data rate of 400 Mbit/s could be realized. For longer transmission distances, this approach can be expanded inexpensively with signal amplifiers and low-loss impedance-matched data cables, or with a multi-mode fiber optic connection.